Reduce Wafer Remnants Through Pre-Assembly Process Optimization

Abstract Wafer fabrication technology has been seeing exponential growth in recent years. This development is driven by the demand for better reliability, superior performance, and lower cost of electronic consumer products. Generally, standard soft-soldering wafer backside metallization multilayer stack AuAs/Ag/Ni/Ag. The present being developed Ti/NiV/Ag as Ti almost neglectable compared to Au. However, this new leads increased remnants remaining on dicing tape after die pickup. reduced effective area surface may cause adhesion issues subsequent attach process. In realizing essential phase, pre-assembly process optimization carried out using some assessment flow data analysis through statistical analyses image measurement skeleton was taken showing a reduction from 70μm 40μm width. method shows that skipping baking will undoubtedly lessen with back metal mounting tape. Without compromising saw quality indeed give remnant. Henceforth, significantly reduce further improve